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Searched refs:SSCG_PLL_BYPASS2_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c225 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK)) in decode_sscg_pll()
587 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); in dram_pll_init()
650 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); in dram_pll_init()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock_imx8mq.h357 #define SSCG_PLL_BYPASS2_MASK BIT(4) macro

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