SSCG_PLL_FEEDBACK_DIV_F1_VAL (reference) in projects: u-boot

Searched refs:SSCG_PLL_FEEDBACK_DIV_F1_VAL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A D	clock_imx8mq.c	`598 val \|= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); in dram_pll_init() 610 val \|= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); in dram_pll_init() 622 val \|= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); in dram_pll_init() 634 val \|= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45); in dram_pll_init()`
/u-boot/arch/arm/include/asm/arch-imx8m/
A D	clock_imx8mq.h	`379 #define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ macro`

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