Home
last modified time | relevance | path

Searched refs:SSCG_PLL_OUTPUT_DIV_VAL_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c236 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> in decode_sscg_pll()
592 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
604 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
616 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
628 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | in dram_pll_init()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock_imx8mq.h385 #define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) macro
388 SSCG_PLL_OUTPUT_DIV_VAL_MASK)

Completed in 5 milliseconds