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Searched refs:SSCG_PLL_REF_DIVR2_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c230 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> in decode_sscg_pll()
595 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
607 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
619 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
631 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock_imx8mq.h374 #define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) macro
376 #define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)

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