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Searched refs:STM32_DDR_BASE (Results 1 – 14 of 14) sorted by relevance

/u-boot/arch/arm/mach-stm32mp/
A Dboot_params.c41 if (nt_fw_dtb >= STM32_DDR_BASE) { in board_fdt_blob_setup()
A Dspl.c146 mmu_set_region_dcache_behaviour(STM32_DDR_BASE, in board_init_f()
A DKconfig107 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
A Dcpu.c239 mmu_set_region_dcache_behaviour(STM32_DDR_BASE, in early_enable_caches()
/u-boot/include/configs/
A Dstm32mp1.h22 #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
/u-boot/arch/arm/mach-stm32mp/include/mach/
A Dstm32.h38 #define STM32_DDR_BASE 0xC0000000 macro
/u-boot/arch/arm/mach-stm32mp/cmd_stm32prog/
A Dcmd_stm32prog.c65 addr = STM32_DDR_BASE; in do_stm32prog()
A Dstm32prog_usb.c93 destination = STM32_DDR_BASE; in stm32prog_cmd_read()
A Dstm32prog_serial.c523 destination = STM32_DDR_BASE; in get_phase_command()
A Dstm32prog.c1173 PHASE_FLASHLAYOUT, STM32_DDR_BASE); in dfu_init_entities()
1457 if (parse_flash_layout(data, STM32_DDR_BASE, 0)) in stm32prog_end_phase()
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_tests.c51 *bufsize = get_ram_size((long *)STM32_DDR_BASE, in get_bufsize()
89 if (value < STM32_DDR_BASE) { in get_addr()
100 *addr = STM32_DDR_BASE; in get_addr()
1284 addr = (u32 *)(STM32_DDR_BASE + in test_read()
1333 addr = (u32 *)(STM32_DDR_BASE + in test_write()
A Dstm32mp1_ram.c203 priv->info.base = STM32_DDR_BASE; in stm32mp1_ddr_probe()
/u-boot/board/dhelectronics/dh_stm32mp1/
A Dboard.c585 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; in board_init()
/u-boot/board/st/stm32mp1/
A Dstm32mp1.c645 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; in board_init()

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