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Searched refs:STM32_RCC_BASE (Results 1 – 6 of 6) sorted by relevance

/u-boot/board/st/stm32mp1/
A Dspl.c37 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) in board_debug_uart_init()
38 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) in board_debug_uart_init()
/u-boot/arch/arm/mach-stm32mp/
A Dcpu.c27 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
28 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
29 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
30 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
31 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
A Dpsci.c21 #define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
/u-boot/arch/arm/mach-stm32mp/include/mach/
A Dstm32.h17 #define STM32_RCC_BASE 0x50000000 macro
/u-boot/board/dhelectronics/dh_stm32mp1/
A Dboard.c568 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR); in board_init_fmc2()
569 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR); in board_init_fmc2()
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_ram.c201 priv->rcc = STM32_RCC_BASE; in stm32mp1_ddr_probe()

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