Searched refs:SW3 (Results 1 – 21 of 21) sorted by relevance
| /u-boot/board/freescale/p1010rdb/ |
| A D | README.P1010RDB-PB | 66 SW3[1:8]= 10010000
73 SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
74 SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
75 SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
76 SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
152 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
156 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
161 Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
167 set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
174 set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
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| /u-boot/board/freescale/ls1088a/ |
| A D | README | 18 SW3 1111 0010
25 SW3 1111 0010
32 SW3 1111 0010
91 SW3 to SW12 are identical for all boot source
93 SW3 0010 0100
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| /u-boot/doc/ |
| A D | README.mpc85xxcds | 134 SW3=11101111
142 frequency can be changed by setting SW3:
146 SW3=XX00XXXX == CORE:CCB 2:1
159 SW3=00001000
173 SW3=11001000 (8X) (2:1)
176 SW3=X000XXXX == CORE:CCB 4:1
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| /u-boot/board/myir/mys_6ulx/ |
| A D | README | 22 SW3 -> 0
47 SW3 -> 0
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| /u-boot/board/freescale/ls1028a/ |
| A D | README | 15 SW3: 1111_0000
20 SW3: 1111_0000
25 SW3: 1111_0000
86 SW3 : 0000_0010
98 SW3 : 0000_0010
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| /u-boot/board/freescale/t102xrdb/ |
| A D | README | 194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
202 via DIP-switch: set SW3[5:7] = '100'
205 via DIP-switch: set SW3[5:7] = '100'
210 via DIP-Switch: set SW3[5:7] = '000'
213 via DIP-switch: set SW3[5:7] = '000'
223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
250 SW3[3] = '1' for SD card(or 'switch sd' by software)
251 SW3[3] = '0' for eMMC (or 'switch emmc' by software)
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| /u-boot/board/freescale/t104xrdb/ |
| A D | README | 288 SW3: 11100001
293 SW3: 11110001
298 SW3: 11100001
303 SW3: 11100001
310 SW3: 11100001
315 SW3: 11110001
320 SW3: 11100001
325 SW3: 11100001
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| /u-boot/board/phytec/pfla02/ |
| A D | README | 21 The dip switch "SW3" on the board let choose the boot device.
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| /u-boot/include/power/ |
| A D | mc34vr500_pmic.h | 167 SW3, enumerator
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| /u-boot/board/sbc8548/ |
| A D | README | 216 SW3.1 CFG_HOST_AGT0 1* 0
217 SW3.2 CFG_HOST_AGT1 1* 0
218 SW3.3 CFG_HOST_AGT2 1* 0
219 SW3.4 CFG_IO_PORTS0 1* 0
220 SW3.5 CFG_IO_PORTS0 1 0*
221 SW3.6 CFG_IO_PORTS0 1 0*
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| /u-boot/board/freescale/t208xrdb/ |
| A D | README | 148 SW3[1:8] = '11100001'
159 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
164 via DIP-switch: set SW3[5:7] = '100'
168 via DIP-Switch: set SW3[5:7] = '000'
178 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
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| /u-boot/board/freescale/mpc832xemds/ |
| A D | README | 17 SW3 is switch 18 as silk-screened onto the board.
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
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| /u-boot/doc/board/freescale/ |
| A D | b4860qds.rst | 143 SW3 OFF OFF OFF ON OFF OFF ON OFF
158 SW3 [1:4] = 0001
164 SW3 [1:4] = 1000
176 SW3 OFF OFF OFF ON OFF OFF ON OFF
191 SW3 [1:4] = 0001
197 SW3 [1:4] = 1000
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| /u-boot/arch/arm/dts/ |
| A D | imx7ulp-evk.dts | 107 sw3_reg: SW3 {
108 regulator-name = "SW3";
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| A D | armada-7040-db.dts | 45 * Boot device: SPI NOR, 0x32 (SW3)
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| A D | armada-7040-db-nand.dts | 45 * Boot device: NAND, 0xE (SW3)
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| A D | ulcb.dtsi | 58 label = "SW3";
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| A D | r8a7794-silk.dts | 52 label = "SW3";
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| A D | armada-388-clearfog.dts | 152 /* The rear SW3 button */
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| /u-boot/board/freescale/mpc837xemds/ |
| A D | README | 26 SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
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| /u-boot/board/ti/ks2_evm/ |
| A D | README | 189 1. Set the SW3 dip switch to "ARM MMC Boot mode" as per instruction at
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