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Searched refs:SYSCLK (Results 1 – 14 of 14) sorted by relevance

/u-boot/doc/
A DREADME.mpc85xxcds150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
184 XXXX0000 == CCB:SYSCLK 16:1
186 XXXX0010 == CCB:SYSCLK 2:1
187 XXXX0011 == CCB:SYSCLK 3:1
188 XXXX0100 == CCB:SYSCLK 4:1
189 XXXX0101 == CCB:SYSCLK 5:1
190 XXXX0110 == CCB:SYSCLK 6:1
192 XXXX1000 == CCB:SYSCLK 8:1
193 XXXX1001 == CCB:SYSCLK 9:1
[all …]
/u-boot/include/dt-bindings/clock/
A Dmicrochip,clock.h14 #define SYSCLK 3 macro
/u-boot/board/freescale/ls1021atwr/
A DREADME88 - System and DDR clock (SYSCLK, DDRCLK)
/u-boot/board/freescale/ls1021aqds/
A DREADME89 - System and DDR clock (SYSCLK, DDRCLK)
/u-boot/board/sbc8548/
A DREADME37 to reflect a different CCB:SYSCLK ratio]
246 D15 SYSCLK 66MHz 33MHz
/u-boot/board/freescale/t104xrdb/
A DREADME115 - System and DDR clock (SYSCLK, “DDRCLK”)
147 - System and DDR clock (SYSCLK, “DDRCLK”)
/u-boot/board/avionic-design/common/
A Dpinmux-config-tamonten-ng.h259 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
260 DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
/u-boot/arch/arm/mach-tegra/tegra114/
A Dpinmux.c230 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/u-boot/board/nvidia/dalmore/
A Dpinmux-config-dalmore.h220 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/u-boot/arch/arm/mach-tegra/tegra30/
A Dpinmux.c225 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/u-boot/board/nvidia/cardhu/
A Dpinmux-config-cardhu.h247 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/u-boot/board/toradex/apalis_t30/
A Dpinmux-config-apalis_t30.h270 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
/u-boot/board/toradex/colibri_t30/
A Dpinmux-config-colibri_t30.h259 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/u-boot/doc/board/freescale/
A Db4860qds.rst107 - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,

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