SYSCTL_CPLL_CFG0_REG (reference) in projects: u-boot

Searched refs:SYSCTL_CPLL_CFG0_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-mtmips/mt7620/
A D	init.c	`41 setbits_32(sysc + SYSCTL_CPLL_CFG0_REG, CPLL_SW_CFG); in cpu_pll_init() 47 clrsetbits_32(sysc + SYSCTL_CPLL_CFG0_REG, PLL_MULT_RATIO_M \| in cpu_pll_init() 107 val = readl(sysc + SYSCTL_CPLL_CFG0_REG); in mt7620_get_clks()`
A D	mt7620.h	`76 #define SYSCTL_CPLL_CFG0_REG 0x54 macro`

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