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Searched refs:SYSCTL_CPLL_CFG1_REG (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/mips/mach-mtmips/mt7620/
A Dinit.c38 clrsetbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPU_CLK_AUX1, CPU_CLK_AUX0); in cpu_pll_init()
44 setbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPLL_PD); in cpu_pll_init()
52 clrbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPLL_PD); in cpu_pll_init()
55 while (!(readl(sysc + SYSCTL_CPLL_CFG1_REG) & CPLL_LD)) in cpu_pll_init()
59 clrbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPU_CLK_AUX1 | CPU_CLK_AUX0); in cpu_pll_init()
101 val = readl(sysc + SYSCTL_CPLL_CFG1_REG); in mt7620_get_clks()
A Dmt7620.h88 #define SYSCTL_CPLL_CFG1_REG 0x58 macro
A Ddram.c77 aux = readl(sysc + SYSCTL_CPLL_CFG1_REG) & in mt7620_dram_init()

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