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Searched refs:TIMING_CFG0_RWT_SHIFT (Results 1 – 18 of 18) sorted by relevance

/u-boot/include/configs/km/
A Dkm-mpc8360.h47 (0 << TIMING_CFG0_RWT_SHIFT))
A Dkm-mpc832x.h50 (0 << TIMING_CFG0_RWT_SHIFT))
A Dkm-mpc8309.h101 (0 << TIMING_CFG0_RWT_SHIFT))
/u-boot/include/configs/
A Dmpc8308_p1m.h67 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A Dve8313.h52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC8323ERDB.h42 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC832XEMDS.h40 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC8308RDB.h63 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A Dids8313.h61 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
A DMPC8313ERDB_NOR.h73 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC8313ERDB_NAND.h102 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC8315ERDB.h58 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC837XEMDS.h69 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A DMPC837XERDB.h85 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A Dhrcon.h52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
A Dstrider.h52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
/u-boot/drivers/ram/
A Dmpc83xx_sdram.c37 static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1); variable
589 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | in mpc83xx_sdram_probe()
/u-boot/include/
A Dmpc83xx.h1154 #define TIMING_CFG0_RWT_SHIFT 30 macro

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