Home
last modified time | relevance | path

Searched refs:TIMING_CFG1_CASLAT_SHIFT (Results 1 – 15 of 15) sorted by relevance

/u-boot/include/configs/
A Dmpc8308_p1m.h79 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A Dve8313.h64 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC8323ERDB.h54 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC832XEMDS.h52 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC8308RDB.h75 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A Dids8313.h72 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
A DMPC8313ERDB_NOR.h85 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC8313ERDB_NAND.h114 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC8315ERDB.h70 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC837XEMDS.h81 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
A DMPC837XERDB.h97 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
A Dhrcon.h64 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
A Dstrider.h64 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
/u-boot/drivers/ram/
A Dmpc83xx_sdram.c50 static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15); variable
688 mcas_latency << TIMING_CFG1_CASLAT_SHIFT | in mpc83xx_sdram_probe()
/u-boot/include/
A Dmpc83xx.h1180 #define TIMING_CFG1_CASLAT_SHIFT 16 macro

Completed in 25 milliseconds