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Searched refs:TIMING_CFG1_PRETOACT_SHIFT (Results 1 – 19 of 19) sorted by relevance

/u-boot/include/configs/km/
A Dkm-mpc8360.h56 (3 << TIMING_CFG1_PRETOACT_SHIFT))
A Dkm-mpc832x.h59 (3 << TIMING_CFG1_PRETOACT_SHIFT))
A Dkm-mpc8309.h110 (3 << TIMING_CFG1_PRETOACT_SHIFT))
/u-boot/include/configs/
A Dmpc8308_p1m.h76 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
A Dve8313.h61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC8323ERDB.h51 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC832XEMDS.h49 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC8308RDB.h72 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
A Dids8313.h69 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
A DMPC8313ERDB_NOR.h82 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC8313ERDB_NAND.h111 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC8315ERDB.h67 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC837XEMDS.h78 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
A DMPC837XERDB.h94 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
A Dhrcon.h61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
A Dstrider.h61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
/u-boot/board/tqc/tqm834x/
A Dtqm834x.c359 (4 << TIMING_CFG1_PRETOACT_SHIFT) | in set_ddr_config()
/u-boot/drivers/ram/
A Dmpc83xx_sdram.c47 static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3); variable
683 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT | in mpc83xx_sdram_probe()
/u-boot/include/
A Dmpc83xx.h1174 #define TIMING_CFG1_PRETOACT_SHIFT 28 macro

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