Searched refs:TRAINING_SW_1_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A D	mv_ddr_regs.h	245 #define TRAINING_SW_1_REG 0x15b4 macro
A D	ddr3_training_leveling.c	249 TRAINING_SW_1_REG, (1 << 16), (1 << 16))); in ddr3_tip_dynamic_read_leveling() 728 TRAINING_SW_1_REG, (1 << 16), (1 << 16))); in ddr3_tip_dynamic_per_bit_read_leveling()

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