Searched refs:TRAINING_SW_2_REG (Results 1 – 3 of 3) sorted by relevance
| /u-boot/drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_leveling.c | 165 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_read_leveling()
246 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
537 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_per_bit_read_leveling()
725 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
1023 TRAINING_SW_2_REG, 0x5, 0x7)); in ddr3_tip_dynamic_write_leveling()
1028 TRAINING_SW_2_REG, 0x4, 0x7)); in ddr3_tip_dynamic_write_leveling()
1468 TRAINING_SW_2_REG, 0x1, 0x5)); in ddr3_tip_dynamic_write_leveling_seq()
1696 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_SW_2_REG, in mv_ddr_rl_dqs_burst()
1703 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_SW_2_REG, in mv_ddr_rl_dqs_burst()
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| A D | mv_ddr_regs.h | 247 #define TRAINING_SW_2_REG 0x15b8 macro
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| A D | ddr3_training.c | 864 TRAINING_SW_2_REG, 0x100, 0x100)); in ddr3_pre_algo_config()
872 TRAINING_SW_2_REG, 0x0, 0x2)); in ddr3_pre_algo_config()
896 TRAINING_SW_2_REG, 0x0, 0x100)); in ddr3_post_algo_config()
1852 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1867 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
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