Searched refs:TSR_WIS (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
A D	cpu.c	363 mtspr(SPRN_TSR, TSR_WIS); in reset_85xx_watchdog()
/u-boot/arch/powerpc/include/asm/
A D	processor.h	417 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ macro

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