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Searched refs:TTBCR_IRGN0_WT (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dcpu.c60 #define TTBCR_IRGN0_WT (2 << 8) macro
/u-boot/arch/arm/lib/
A Dcache-cp15.c148 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT; in mmu_setup()
/u-boot/arch/arm/include/asm/
A Dsystem.h434 #define TTBCR_IRGN0_WT (2 << 8) macro

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