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Searched refs:TZPCDECPROT_0_SET_BASE (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dconfig.h102 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) macro
136 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) macro
185 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) macro
250 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) macro
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dlowlevel.S229 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */

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