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Searched refs:UART_PAD_CTRL (Results 1 – 25 of 87) sorted by relevance

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/u-boot/board/myir/mys_6ulx/
A Dmys_6ulx.c31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ macro
37 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
38 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
42 MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
43 MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
45 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/ccv/xpress/
A Dxpress.c34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ macro
113 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
115 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
116 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
125 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
126 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
127 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
128 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
132 MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
137 MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
[all …]
/u-boot/board/barco/platinum/
A Dplatinum_titanium.c73 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
81 MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87 MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
88 MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
A Dplatinum_picon.c71 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
72 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
84 MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
86 MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/ea/mx7ulp_com/
A Dmx7ulp_com.c17 #define UART_PAD_CTRL (PAD_CTL_PUS_UP) macro
27 MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
28 MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/novtech/meerkat96/
A Dmeerkat96.c20 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ macro
25 MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
26 MX7D_PAD_SD1_WP__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/phytec/pcl063/
A Dpcl063.c33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ macro
39 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
45 MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
46 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
47 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/toradex/colibri-imx8x/
A Dcolibri-imx8x.c26 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ macro
32 SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
35 SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/tbs/tbs2910/
A Dtbs2910.c25 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ macro
30 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
31 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
35 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
36 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/mx7ulp_evk/
A Dmx7ulp_evk.c18 #define UART_PAD_CTRL (PAD_CTL_PUS_UP) macro
28 MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
29 MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/google/imx8mq_phanbell/
A Dimx8mq_phanbell.c27 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
36 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
37 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/imx8mq_evk/
A Dimx8mq_evk.c32 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
41 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
42 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/imx8mn_evk/
A Dspl.c65 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
69 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
70 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/beacon/imx8mn/
A Dspl.c71 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
80 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
81 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/somlabs/visionsom-6ull/
A Dvisionsom-6ull.c31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ macro
43 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/phytec/phycore_imx8mm/
A Dspl.c67 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
71 IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
72 IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/mx6ullevk/
A Dmx6ullevk.c27 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ macro
39 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/barco/titanium/
A Dtitanium.c30 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ macro
51 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
57 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
62 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/imx8qm_mek/
A Dimx8qm_mek.c24 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ macro
30 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
31 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/advantech/imx8qm_rom7720_a1/
A Dimx8qm_rom7720_a1.c25 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ macro
31 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
32 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/imx8mp_evk/
A Dimx8mp_evk.c23 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
27 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
28 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/freescale/mx6sllevk/
A Dmx6sllevk.c27 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ macro
39 MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/toradex/apalis-imx8/
A Dapalis-imx8.c26 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ macro
32 SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/phytec/phycore_imx8mp/
A Dspl.c79 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) macro
83 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
84 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/u-boot/board/toradex/apalis-imx8x/
A Dapalis-imx8x.c26 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ macro
32 SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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