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Searched refs:ULL (Results 1 – 25 of 29) sorted by relevance

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/u-boot/include/
A Ddiv64.h72 ___m = (~0ULL / ___b) * ___p; \
73 ___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b; \
76 ___x = ~0ULL / ___b * ___b - 1; \
88 if (~0ULL % (___b / (___b & -___b)) == 0) { \
91 ___m = ~0ULL / (___b / (___b & -___b)); \
105 ___m = (~0ULL / ___b) * ___p; \
106 ___m += ((~0ULL % ___b + 1) * ___p) / ___b; \
/u-boot/include/linux/
A Dconst.h26 #define _ULL(x) (_AC(x, ULL))
32 #define ULL(x) (_ULL(x)) macro
A Dsizes.h49 #define SZ_4G _AC(0x100000000, ULL)
A Dbitfield.h75 __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: "); \
89 __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
A Dbitops.h38 (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
A Dkernel.h16 #define LLONG_MAX ((long long)(~0ULL>>1))
18 #define ULLONG_MAX (~0ULL)
35 #define U64_MAX ((u64)~0ULL)
A Dzstd.h757 #define ZSTD_CONTENTSIZE_UNKNOWN (0ULL - 1)
758 #define ZSTD_CONTENTSIZE_ERROR (0ULL - 2)
/u-boot/arch/arm/include/asm/
A Dgic-v3.h21 #define GIC_BASER_CACHE_NCNB 0ULL
22 #define GIC_BASER_CACHE_SAMEASINNER 0ULL
31 #define GIC_BASER_NONSHAREABLE 0ULL
/u-boot/board/somlabs/visionsom-6ull/
A DMAINTAINERS1 VISIONSOM-6ULL BOARD
/u-boot/fs/btrfs/kernel-shared/
A Dbtrfs_tree.h85 #define BTRFS_DEV_STATS_OBJECTID 0ULL
131 #define BTRFS_DEV_REPLACE_DEVID 0ULL
1241 #define BTRFS_FEATURE_COMPAT_SUPP 0ULL
1242 #define BTRFS_FEATURE_COMPAT_SAFE_SET 0ULL
1243 #define BTRFS_FEATURE_COMPAT_SAFE_CLEAR 0ULL
1249 #define BTRFS_FEATURE_COMPAT_RO_SAFE_SET 0ULL
1250 #define BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR 0ULL
1268 #define BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR 0ULL
/u-boot/arch/arm/dts/
A Dimx6ull-phytec-phycore-som.dtsi10 model = "PHYTEC phyCORE-i.MX6 ULL";
A Dimx6ull-phytec-segin.dtsi10 model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
A Dimx6ull-phytec-segin-ff-rdk-emmc.dts14 model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
A Dimx6ull-somlabs-visionsom.dts13 model = "SoMLabs VisionSOM-6ULL";
/u-boot/board/armltd/integrator/
A Dtimer.c82 total_count = 0ULL; in timer_init()
/u-boot/drivers/net/octeontx/
A Dnicvf_queues.h24 #define RBDR_SIZE0 0ULL /* 8K entries */
32 #define SND_QUEUE_SIZE0 0ULL /* 1K entries */
40 #define CMP_QUEUE_SIZE0 0ULL /* 1K entries */
/u-boot/drivers/net/octeontx2/
A Drvu.h13 #define Q_SIZE_16 0ULL /* 16 entries */
A Dnix.h41 #define NPA_POOL_RX 0ULL
48 #define NIX_CQ_RX 0ULL
/u-boot/drivers/watchdog/
A Docteontx_wdt.c85 writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET); in octeontx_wdt_reset()
/u-boot/scripts/dtc/
A Ddtc-lexer.l169 <V1>([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? {
A Ddtc-parser.y382 uint64_t val = ~0ULL >> (64 - $1.bits);
/u-boot/lib/lzma/
A DTypes.h72 #define UINT64_CONST(n) n ## ULL
/u-boot/arch/x86/cpu/apollolake/
A Dacpi.c97 gnvs->pm1i = ~0ULL; in acpi_create_gnvs()
/u-boot/fs/btrfs/
A Dbtrfs.c105 printf("%10llu ", 0ULL); in show_dir()
/u-boot/arch/arm/mach-imx/mx6/
A DKconfig65 bool "i.MX 6ULL SoC support"
189 bool "Variscite imx6ULL dart(DART-SOM-6ULL)"

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