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Searched refs:VPLL0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_rk3308.c63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
/u-boot/arch/arm/include/asm/arch-rk3308/
A Dcru_rk3308.h34 VPLL0, enumerator

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