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Searched refs:V_NS16550_CLK (Results 1 – 16 of 16) sorted by relevance

/u-boot/include/configs/
A Dti_omap3_common.h28 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ macro
29 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
A Dbcmstb.h108 #define V_NS16550_CLK 81000000 macro
113 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
A Dsniper.h31 #define V_NS16550_CLK 48000000 macro
88 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
A Dtao3530.h43 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ macro
47 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
A Dnokia_rx51.h58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ macro
62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
A Dam3517_crane.h48 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ macro
52 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
A Dtegra186-common.h14 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ macro
A Dtegra210-common.h15 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ macro
A Dtegra114-common.h13 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ macro
A Dtegra30-common.h14 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ macro
A Dtegra124-common.h15 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ macro
A Dtegra20-common.h14 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ macro
A Dtegra-common.h32 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/u-boot/board/timll/devkit8000/
A Ddevkit8000.c54 .clock = V_NS16550_CLK,
/u-boot/board/lg/sniper/
A Dsniper.c37 .clock = V_NS16550_CLK,
/u-boot/board/isee/igep00x0/
A Digep00x0.c35 .clock = V_NS16550_CLK,

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