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Searched refs:WL (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/ddr/microchip/
A Dddr2.c42 writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); in ddr2_phy_init()
151 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()
153 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()
168 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
196 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
A Dddr2_timing.h19 #define WL 4 macro
/u-boot/arch/arm/dts/
A Dsun50i-a64-amarula-relic.dts63 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
150 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */
A Dsun7i-a20-bananapi-m1-plus.dts91 reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
A Dsun8i-a83t-bananapi-m3.dts106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
A Dsun8i-a83t-tbs-a711.dts120 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
A Dam5729-beagleboneai.dts156 <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
A Dsun8i-a83t-cubietruck-plus.dts144 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
A Dsun9i-a80-cubieboard4.dts128 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
A Dsun9i-a80-optimus.dts106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */

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