WR_LVL_PH_SEL_OFFS (reference) in projects: u-boot

Searched refs:WR_LVL_PH_SEL_OFFS (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A D	mv_ddr_regs.h	`390 #define WR_LVL_PH_SEL_OFFS 6 macro`
A D	ddr3_training_leveling.c	`1072 temp = (reg_data >> WR_LVL_PH_SEL_OFFS) & WR_LVL_PH_SEL_PHASE1; in ddr3_tip_dynamic_write_leveling() 1073 reg_data &= ~(WR_LVL_PH_SEL_MASK << WR_LVL_PH_SEL_OFFS); in ddr3_tip_dynamic_write_leveling() 1074 reg_data \|= (temp << WR_LVL_PH_SEL_OFFS); in ddr3_tip_dynamic_write_leveling()`

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