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Searched refs:WTCSR (Results 1 – 3 of 3) sorted by relevance

/u-boot/board/renesas/grpeach/
A Dgrpeach.c15 #define WTCSR 0x00 macro
51 writew(0xa578, RZA1_WDT_BASE + WTCSR); in reset_cpu()
A Dlowlevel_init.S12 #define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ macro
75 write16 WTCSR, WTCSR_D
/u-boot/arch/sh/include/asm/
A Dcpu_sh7750.h93 #define WTCSR 0xFFC0000C macro

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