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Searched refs:XCHAL_HAVE_TLBS (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/xtensa/include/asm/arch-dc232b/
A Dcore.h401 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/u-boot/arch/xtensa/include/asm/arch-dc233c/
A Dcore.h431 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/u-boot/arch/xtensa/include/asm/arch-de212/
A Dcore.h552 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro

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