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Searched refs:XCHAL_VECBASE_RESET_VADDR (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/configs/
A Dxtfpga.h34 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
82 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
/u-boot/arch/xtensa/include/asm/
A Daddrspace.h27 #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \
/u-boot/arch/xtensa/include/asm/arch-dc232b/
A Dcore.h332 #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ macro
/u-boot/arch/xtensa/include/asm/arch-dc233c/
A Dcore.h362 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
/u-boot/arch/xtensa/include/asm/arch-de212/
A Dcore.h466 #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ macro
/u-boot/arch/xtensa/cpu/
A Dstart.S120 movi a3, XCHAL_VECBASE_RESET_VADDR /* VECBASE reset value */

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