XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (reference) in projects: u-boot

Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/arm/mach-tegra/tegra210/
A D	xusb-padctl.c	`193 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3) macro 325 value \|= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; in pcie_phy_enable() 469 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; in tegra_xusb_padctl_exit()`

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