Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (Results 1 – 1 of 1) sorted by relevance
196 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0) macro273 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; in pcie_phy_enable()466 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; in tegra_xusb_padctl_exit()
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