Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (Results 1 – 1 of 1) sorted by relevance
194 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1) macro277 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; in pcie_phy_enable()467 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; in tegra_xusb_padctl_exit()
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