Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL2 (Results 1 – 1 of 1) sorted by relevance
| /u-boot/arch/arm/mach-tegra/tegra210/ |
| A D | xusb-padctl.c | 198 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 macro
237 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
240 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
251 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
253 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
295 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
305 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
307 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
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