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Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/arm/mach-tegra/tegra210/
A Dxusb-padctl.c200 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4) macro
239 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); in pcie_phy_enable()

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