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Searched refs:ZQ_CLK_DIV_EN (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Ddmc_common.c32 val |= ZQ_CLK_DIV_EN; in dmc_config_zq()
A Ddmc_init_ddr3.c533 clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN); in ddr3_mem_ctrl_init()
534 clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN); in ddr3_mem_ctrl_init()
A Dexynos5_setup.h322 #define ZQ_CLK_DIV_EN (1 << 18) macro

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