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Searched refs:_REG (Results 1 – 7 of 7) sorted by relevance

/u-boot/drivers/video/meson/
A Dmeson_vpu_init.c172 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
175 _REG(VIU_OSD1_MATRIX_COEF31_32)); in meson_viu_set_osd_matrix()
178 _REG(VIU_OSD1_MATRIX_COEF40_41)); in meson_viu_set_osd_matrix()
210 _REG(VIU_OSD1_EOTF_CTL + i + 1)); in meson_viu_set_osd_matrix()
268 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
271 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
295 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
301 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
447 priv->io_base + _REG(VPP_MISC)); in meson_vpu_init()
451 priv->io_base + _REG(VPP_MISC)); in meson_vpu_init()
[all …]
A Dmeson_venc.c965 _REG(ENCI_VFIFO2VD_PIXEL_START)) in meson_venc_hdmi_mode_set()
977 _REG(ENCI_VFIFO2VD_LINE_TOP_START)); in meson_venc_hdmi_mode_set()
980 _REG(ENCI_VFIFO2VD_LINE_BOT_START)); in meson_venc_hdmi_mode_set()
1093 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); in meson_venc_hdmi_mode_set()
1101 + _REG(ENCI_DVI_VSO_ELINE_ODD)); in meson_venc_hdmi_mode_set()
1104 + _REG(ENCI_DVI_VSO_END_ODD)); in meson_venc_hdmi_mode_set()
1109 + _REG(ENCI_DVI_VSO_ELINE_EVN)); in meson_venc_hdmi_mode_set()
1112 + _REG(ENCI_DVI_VSO_END_EVN)); in meson_venc_hdmi_mode_set()
1212 _REG(ENCP_VIDEO_HAVON_BEGIN)) in meson_venc_hdmi_mode_set()
1225 + _REG(ENCP_VIDEO_VAVON_BLINE)); in meson_venc_hdmi_mode_set()
[all …]
A Dmeson_plane.c67 priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
70 priv->io_base + _REG(VPP_OSD_SCI_WH_M1)); in meson_vpp_setup_interlace_vscaler_osd1()
81 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
90 priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
96 writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
97 writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
135 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_vpu_setup_plane()
142 priv->io_base + _REG(VPP_MISC)); in meson_vpu_setup_plane()
161 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_vpu_setup_plane()
212 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_vpu_setup_plane()
[all …]
A Dmeson_registers.h11 #define _REG(reg) ((reg) << 2) macro
/u-boot/drivers/dma/ti/
A Dk3-udma-hwdef.h38 #define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
/u-boot/arch/x86/include/asm/arch-tangier/acpi/
A Dsouthcluster.asl305 Method (_REG, 2, NotSerialized)
510 Method (_REG, 2, NotSerialized)
/u-boot/arch/x86/include/asm/acpi/cros_ec/
A Dec.asl149 Method (_REG, 2, NotSerialized)

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