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/u-boot/arch/arm/include/asm/arch-rockchip/
A Dclock.h52 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
57 .postdiv1 = _postdiv1, \
/u-boot/drivers/clk/rockchip/
A Dclk_rk3036.c36 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
38 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
39 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
40 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
41 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
A Dclk_rk322x.c34 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
36 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
37 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
38 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
39 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
A Dclk_rv1108.c37 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
40 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
41 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
42 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
A Dclk_rk3128.c33 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
35 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
36 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
A Dclk_rk3328.c37 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
40 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
A Dclk_rk3399.c52 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
54 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
55 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
A Dclk_px30.c36 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
41 .postdiv1 = _postdiv1, \

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