| /u-boot/drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 50 #define UNIPHIER_CLK_RATE(_id, _rate) \ argument
55 .fixed_rate = (_rate), \
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 52 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
55 .rate = _rate##U, \
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| /u-boot/drivers/clk/renesas/ |
| A D | renesas-cpg-mssr.h | 80 #define DEF_RATE(_name, _id, _rate) \ argument
81 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
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| /u-boot/drivers/clk/imx/ |
| A D | clk-imx8mm.c | 18 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ argument
20 .rate = (_rate), \
26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
28 .rate = (_rate), \
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| A D | clk-imx8mn.c | 18 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ argument
20 .rate = (_rate), \
26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
28 .rate = (_rate), \
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| A D | clk-imx8mp.c | 18 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ argument
20 .rate = (_rate), \
26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
28 .rate = (_rate), \
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mtk.h | 62 #define FIXED_CLK(_id, _parent, _rate) { \ argument
65 .rate = _rate, \
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | clock.h | 190 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ argument
192 .clk = (_rate), \
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| A D | clock_imx8mm.h | 15 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
17 .rate = (_rate), \
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_px30.c | 36 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
39 .rate = _rate##U, \
48 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
50 .rate = _rate##U, \
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| A D | clk_rk3308.c | 35 #define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
37 .rate = _rate##U, \
|