| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mtk.h | 122 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ argument
126 .mux_shift = _shift, \
135 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ argument
136 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
138 #define MUX(_id, _parents, _reg, _shift, _width) { \ argument
141 .mux_shift = _shift, \
150 _mux_clr_ofs, _shift, _width, _gate, \ argument
158 .mux_shift = _shift, \
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| A D | clk-mt8512.c | 611 #define GATE_TOP0(_id, _parent, _shift) { \ argument
615 .shift = _shift, \
619 #define GATE_TOP1(_id, _parent, _shift) { \ argument
623 .shift = _shift, \
676 #define GATE_INFRA0(_id, _parent, _shift) { \ argument
680 .shift = _shift, \
688 .shift = _shift, \
696 .shift = _shift, \
704 .shift = _shift, \
712 .shift = _shift, \
[all …]
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| A D | clk-mt7629.c | 427 #define GATE_INFRA(_id, _parent, _shift) { \ argument
431 .shift = _shift, \
456 #define GATE_PERI0(_id, _parent, _shift) { \ argument
460 .shift = _shift, \
464 #define GATE_PERI1(_id, _parent, _shift) { \ argument
468 .shift = _shift, \
505 .shift = _shift, \
509 #define GATE_ETH0(_id, _parent, _shift) \ argument
512 #define GATE_ETH1(_id, _parent, _shift) \ argument
533 .shift = _shift, \
[all …]
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| A D | clk-mt8516.c | 578 #define GATE_TOP0(_id, _parent, _shift) { \ argument
582 .shift = _shift, \
586 #define GATE_TOP1(_id, _parent, _shift) { \ argument
590 .shift = _shift, \
594 #define GATE_TOP2(_id, _parent, _shift) { \ argument
598 .shift = _shift, \
606 .shift = _shift, \
610 #define GATE_TOP3(_id, _parent, _shift) { \ argument
614 .shift = _shift, \
622 .shift = _shift, \
[all …]
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| A D | clk-mt7622.c | 376 #define GATE_INFRA(_id, _parent, _shift) { \ argument
380 .shift = _shift, \
406 #define GATE_PERI0(_id, _parent, _shift) { \ argument
410 .shift = _shift, \
414 #define GATE_PERI1(_id, _parent, _shift) { \ argument
418 .shift = _shift, \
463 #define GATE_PCIE(_id, _parent, _shift) { \ argument
467 .shift = _shift, \
496 #define GATE_ETH(_id, _parent, _shift) { \ argument
500 .shift = _shift, \
[all …]
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| A D | clk-mt8518.c | 1301 #define GATE_TOP0(_id, _parent, _shift) { \ argument
1305 .shift = _shift, \
1313 .shift = _shift, \
1321 .shift = _shift, \
1329 .shift = _shift, \
1337 .shift = _shift, \
1345 .shift = _shift, \
1353 .shift = _shift, \
1361 .shift = _shift, \
1369 .shift = _shift, \
[all …]
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| A D | clk-mt7623.c | 590 #define GATE_INFRA(_id, _parent, _shift) { \ argument
594 .shift = _shift, \
632 #define GATE_PERI0(_id, _parent, _shift) { \ argument
636 .shift = _shift, \
640 #define GATE_PERI1(_id, _parent, _shift) { \ argument
644 .shift = _shift, \
701 #define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \ argument
705 .shift = _shift, \
709 #define GATE_ETH_HIF0(_id, _parent, _shift) \ argument
710 GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
[all …]
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| A D | clk-mt8183.c | 629 #define GATE_INFRA0(_id, _parent, _shift) { \ argument
633 .shift = _shift, \
637 #define GATE_INFRA1(_id, _parent, _shift) { \ argument
641 .shift = _shift, \
645 #define GATE_INFRA2(_id, _parent, _shift) { \ argument
649 .shift = _shift, \
653 #define GATE_INFRA3(_id, _parent, _shift) { \ argument
657 .shift = _shift, \
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| /u-boot/drivers/pinctrl/mtmips/ |
| A D | pinctrl-mtmips-common.h | 41 #define GRP(_name, _funcs, _reg, _shift, _mask) \ argument
42 { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
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| /u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| A D | clk-core.h | 299 #define DIVIDER(_offset, _shift, _width) \ argument
302 .shift = (_shift), \
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
312 .shift = (_shift), \
350 #define SELECTOR(_offset, _shift, _width) \ argument
353 .shift = (_shift), \
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| /u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| A D | clk-core.h | 299 #define DIVIDER(_offset, _shift, _width) \ argument
302 .shift = (_shift), \
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
312 .shift = (_shift), \
350 #define SELECTOR(_offset, _shift, _width) \ argument
353 .shift = (_shift), \
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| /u-boot/drivers/clk/microchip/ |
| A D | mpfs_clk_cfg.c | 105 #define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ argument
108 .cfg.shift = _shift, \
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| A D | mpfs_clk_periph.c | 114 #define CLK_PERIPH(_id, _name, _shift, _flags) { \ argument
117 .periph.shift = _shift, \
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| /u-boot/drivers/clk/kendryte/ |
| A D | clk.c | 148 #define DIV_FLAGS(id, _off, _shift, _width, _flags) \ argument
151 .shift = (_shift), \
254 #define MUX_PARENTS(id, parents, _off, _shift, _width) \ argument
259 .shift = (_shift), \
277 #define PLL(_off, _shift, _width) { \ argument
280 .shift = (_shift), \
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| /u-boot/arch/arm/mach-tegra/tegra124/ |
| A D | xusb-padctl.c | 85 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
89 .shift = _shift, \
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| /u-boot/arch/arm/mach-tegra/tegra210/ |
| A D | xusb-padctl.c | 65 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
69 .shift = _shift, \
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