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/u-boot/arch/mips/mach-octeon/
A Dlowlevel_init.S24 dmfc0 a0, COP0_CVMMEMCTL_REG
25 dins a0, zero, 0, 9
36 dmtc0 a0, COP0_CVMMEMCTL_REG
39 dmfc0 a0, COP0_CVMCTL_REG
41 dmtc0 a0, COP0_CVMCTL_REG
70 ld a0, 0(t0)
74 sd a0, 0(t1)
113 dmfc0 a0, COP0_CVMMEMCTL_REG
114 dins a0, zero, 0, 9
116 dmtc0 a0, COP0_CVMMEMCTL_REG
[all …]
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S74 li a0, 0
79 1: cache INDEX_STORE_TAG_I, 0(a0)
80 addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE
81 bne a0, a1, 1b
85 li a0, 0
90 2: cache INDEX_STORE_TAG_D, 0(a0)
91 addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
92 bne a0, a1, 2b
109 and t0, a0, a2
113 cache INDEX_STORE_TAG_D, 0(a0)
[all …]
/u-boot/arch/riscv/lib/
A Dsetjmp.S10 #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
11 #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
13 #define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
14 #define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
34 li a0, 0
58 mv a0, a1
62 li a0, 1
A Dcrt0_riscv_efi.S160 SAVE_LONG(a0, 0)
164 lla a0, ImageBase
167 bne a0, zero, 0f
170 LOAD_LONG(a0, 0)
/u-boot/arch/xtensa/cpu/
A Dstart.S82 movi a0, 0
227 movi a0, 0
296 callx0 a0
303 ssl a0
304 movi a0, 1
305 sll a0, a0
361 callx0 a0
455 addx4 a0, a2, a0
456 l32i a0, a0, 0
459 callx0 a0
[all …]
/u-boot/arch/riscv/cpu/
A Dstart.S50 mv tp, a0
102 mv a0, sp
109 mv s0, a0
117 mv sp, a0
213 mv s0, a0
234 beqz a0, 1f
235 mv a1, a0
245 mv a0, zero
376 beqz a0, 1f
377 mv a1, a0
[all …]
/u-boot/board/imgtec/boston/
A Dlowlevel_init.S25 PTR_LA a0, msg_ddr_cal
33 PTR_LA a0, msg_ddr_ok
44 ld k1, 0(a0)
47 lw k1, 0(a0)
49 lw k1, 4(a0)
/u-boot/arch/m68k/cpu/mcf5227x/
A Dstart.S212 move.b %d0, (%a0)
216 move.b (%a0), %d0
299 jmp (%a0)
409 move.l %a0, %a3
421 move.l %a0, %a1
431 move.l %a0, %a1
433 move.l %a0, %d1
443 move.l %a0, %a1
447 move.l %a0, %a2
453 add.l %a0,%d1
[all …]
/u-boot/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S18 li a0, 0xbd001f00
20 sw zero, 0x4(a0) /* Place where the number of passing taps are saved. */
21 sw zero, 0x14(a0) /* Place where the last pass tap value is stored */
23 sw a1, 0x10(a0) /* Place where the First pass tap value is stored */
26 li a0, CKSEG1ADDR(AR71XX_RESET_BASE) /* RESET_BASE_ADDRESS */
27 lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */
30 sw a1, 0x1c(a0)
35 sw a1, 0x1c(a0) /* Taking the RTC out of RESET */
38 li a0, CKSEG1ADDR(QCA956X_RTC_BASE) /* RTC_BASE_ADDRESS */
40 sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */
[all …]
/u-boot/arch/m68k/cpu/mcf5445x/
A Dstart.S284 jmp (%a0)
320 jmp (%a0)
432 jmp (%a0)
537 move.l %a0, %a3
549 move.l %a0, %a1
559 move.l %a0, %a1
561 move.l %a0, %d1
571 move.l %a0, %a1
575 move.l %a0, %a2
581 add.l %a0,%d1
[all …]
/u-boot/fs/zfs/
A Dzfs_fletcher.c40 uint64_t a0, b0, a1, b1; in fletcher_2_endian() local
42 for (a0 = b0 = a1 = b1 = 0; ip < ipend; ip += 2) { in fletcher_2_endian()
43 a0 += zfs_to_cpu64(ip[0], endian); in fletcher_2_endian()
45 b0 += a0; in fletcher_2_endian()
49 zcp->zc_word[0] = cpu_to_zfs64(a0, endian); in fletcher_2_endian()
/u-boot/arch/m68k/cpu/mcf532x/
A Dstart.S21 moveml %d0-%d7/%a0-%a6,%sp@;
118 move.w (%a0), %d0
121 move.w %d0, (%a0)
188 move.l %a0, %a3
200 move.l %a0, %a1
210 move.l %a0, %a1
212 move.l %a0, %d1
222 move.l %a0, %a1
226 move.l %a0, %a2
232 add.l %a0,%d1
[all …]
/u-boot/arch/arm/mach-tegra/
A Dpmc.c60 if (res.a0) in tegra_pmc_readl()
61 printf("%s(): SMC failed: %lu\n", __func__, res.a0); in tegra_pmc_readl()
78 if (res.a0) in tegra_pmc_writel()
79 printf("%s(): SMC failed: %lu\n", __func__, res.a0); in tegra_pmc_writel()
/u-boot/arch/m68k/cpu/mcf52x2/
A Dstart.S19 moveml %d0-%d7/%a0-%a6,%sp@; \
143 move.l (%a0)+, (%a2)+
144 cmp.l %a0, %a1
252 move.l %a0, %a3
263 move.l %a0, %a1
273 move.l %a0, %a1
275 move.l %a0, %d1
285 move.l %a0, %a1
289 move.l %a0, %a2
295 add.l %a0,%d1
[all …]
/u-boot/arch/m68k/cpu/mcf523x/
A Dstart.S18 moveml %d0-%d7/%a0-%a6,%sp@;
21 moveml %sp@,%d0-%d7/%a0-%a6; \
173 move.l %a0, %a3
185 move.l %a0, %a1
195 move.l %a0, %a1
197 move.l %a0, %d1
207 move.l %a0, %a1
211 move.l %a0, %a2
217 add.l %a0,%d1
223 move.l %a0, %a1
[all …]
/u-boot/arch/m68k/cpu/mcf530x/
A Dstart.S19 moveml %d0-%d7/%a0-%a6,%sp@
23 moveml %sp@,%d0-%d7/%a0-%a6;
173 move.l %a0, %a3
184 move.l %a0, %a1
194 move.l %a0, %a1
196 move.l %a0, %d1
206 move.l %a0, %a1
212 move.l %a0, %a2
218 add.l %a0,%d1
224 move.l %a0, %a1
[all …]
/u-boot/arch/m68k/cpu/mcf547x_8x/
A Dstart.S18 moveml %d0-%d7/%a0-%a6,%sp@;
21 moveml %sp@,%d0-%d7/%a0-%a6; \
178 move.l %a0, %a3
190 move.l %a0, %a1
200 move.l %a0, %a1
202 move.l %a0, %d1
212 move.l %a0, %a1
216 move.l %a0, %a2
222 add.l %a0,%d1
228 move.l %a0, %a1
[all …]
/u-boot/arch/mips/lib/
A Dcache_init.S93 li a0, \mode
268 PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
269 PTR_ADDU a1, a0, v0
270 2: PTR_ADDIU a0, 64
271 f_fill64 a0, -64, zero
272 bne a0, a1, 2b
430 ins t0, a0, 0, 3
432 xor a0, a0, t0
433 andi a0, a0, CONF_CM_CMASK
434 xor a0, a0, t0
[all …]
A Dgenex.S137 mfc0 a0, CP0_STATUS
138 ori a0, STATMASK
139 xori a0, STATMASK
140 mtc0 a0, CP0_STATUS
142 and a0, v1
146 or v0, a0
190 move a0, sp
211 move a0, sp
/u-boot/include/linux/
A Darm-smccc.h63 unsigned long a0; member
94 asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
111 asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
A Dmath64.h194 } rl, rm, rn, rh, a0, b0; in mul_u64_u64_shr() local
197 a0.ll = a; in mul_u64_u64_shr()
200 rl.ll = mul_u32_u32(a0.l.low, b0.l.low); in mul_u64_u64_shr()
201 rm.ll = mul_u32_u32(a0.l.low, b0.l.high); in mul_u64_u64_shr()
202 rn.ll = mul_u32_u32(a0.l.high, b0.l.low); in mul_u64_u64_shr()
203 rh.ll = mul_u32_u32(a0.l.high, b0.l.high); in mul_u64_u64_shr()
/u-boot/arch/arm/mach-owl/
A Dsoc.c66 PSCI_VERSION_MAJOR(res.a0), in show_psci_version()
67 PSCI_VERSION_MINOR(res.a0)); in show_psci_version()
/u-boot/drivers/tee/optee/
A Dcore.c33 u32 a0; member
255 switch (OPTEE_SMC_RETURN_GET_RPC_FUNC(param->a0)) { in handle_rpc()
285 param->a0 = OPTEE_SMC_CALL_RETURN_FROM_RPC; in handle_rpc()
301 struct rpc_param param = { .a0 = OPTEE_SMC_CALL_WITH_ARG }; in do_call_with_arg()
308 pdata->invoke_fn(param.a0, param.a1, param.a2, param.a3, in do_call_with_arg()
314 if (OPTEE_SMC_RETURN_IS_RPC(res.a0)) { in do_call_with_arg()
315 param.a0 = res.a0; in do_call_with_arg()
328 return call_err_to_res(res.a0); in do_call_with_arg()
572 static void optee_smccc_smc(unsigned long a0, unsigned long a1, in optee_smccc_smc() argument
578 arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); in optee_smccc_smc()
[all …]
/u-boot/arch/arm/mach-stm32mp/include/mach/
A Dstm32mp1_smc.h48 if (res.a0) { in stm32_smc()
50 __func__, svc, op, res.a0); in stm32_smc()
/u-boot/arch/mips/cpu/
A Dstart.S39 move k1, a0 # preserve a0 in k1
41 li a0, 0 # Use hard register context
278 move a0, zero # a0 <-- boot_flags = 0

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