Searched refs:ahb_reset0_cfg (Results 1 – 13 of 13) sorted by relevance
| /u-boot/arch/arm/mach-sunxi/ |
| A D | cpu_info.c | 27 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); in sunxi_get_ss_bonding_id()
35 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); in sunxi_get_ss_bonding_id()
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| A D | dram_sun8i_a83t.c | 400 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
412 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
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| A D | clock_sun6i.c | 58 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
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| A D | dram_sun9i.c | 275 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
282 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
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| A D | dram_sun8i_a23.c | 70 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
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| A D | dram_sun8i_a33.c | 316 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
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| A D | dram_sunxi_dw.c | 427 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
455 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
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| A D | dram_sun6i.c | 47 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | clock_sun9i.h | 94 u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ member
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| A D | clock_sun8i_a83t.h | 120 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ member
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| A D | clock_sun6i.h | 158 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ member
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| /u-boot/drivers/mmc/ |
| A D | sunxi_mmc.c | 544 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); in sunxi_mmc_init()
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| /u-boot/board/sunxi/ |
| A D | board.c | 397 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); in nand_clock_setup()
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