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/u-boot/doc/
A DREADME.displaying-bmps6 make sure all data is properly aligned, and in many situations simply choosing
7 a 32 bit aligned address is enough to ensure proper alignment. This is not
23 When placed in an aligned address such as 0x80a00000, char signature offsets
26 access is generated at a non-32-bit-aligned address, causing a data abort.
27 The proper alignment for BMP images is therefore: 32-bit-aligned-address + 2.
A DREADME.arm-caches38 memory DMA buffer) should be aligned to cache-line boundary both at
40 - If the buffer is not cache-line aligned invalidation will be restricted
41 to the aligned part. That is, one cache-line at the respective boundary
A DREADME.unaligned-memory-access.txt97 to pad structures so that accesses to fields are suitably aligned (assuming
101 parameters to a naturally aligned scheme, based on the size of the type of
171 16-bit-aligned addresses. It is up to the caller to ensure this alignment or
227 aligned memory, using these macros to access unaligned memory can be costly in
/u-boot/include/
A Dbinman_sym.h37 __attribute__((aligned(4), unused, section(".binman_sym")))
48 __attribute__((aligned(4), unused, section(".binman_sym")))
62 __attribute__((aligned(4), weak, unused, \
A Dscsi.h18 __attribute__((aligned(ARCH_DMA_MINALIGN)));
/u-boot/drivers/net/
A Dftmac100.h103 } __attribute__ ((aligned(16)));
124 } __attribute__ ((aligned(16)));
A Dnatsemi.c219 static BufferDesc txd __attribute__ ((aligned(4)));
220 static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
222 static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
224 __attribute__ ((aligned(4)));
A Dns8382x.c245 static BufferDesc txd __attribute__ ((aligned(8)));
246 static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
247 static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
249 __attribute__ ((aligned(8)));
A Dxilinx_axi_emac.c78 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
124 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
125 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
/u-boot/arch/m68k/include/asm/
A Dtypes.h12 } __attribute__((aligned(16))) vector128;
/u-boot/drivers/usb/host/
A Dohci.h71 } __attribute__((aligned(ED_ALIGNMENT)));
129 } __attribute__((aligned(TD_ALIGNMENT)));
147 } __attribute__((aligned(256)));
191 } __attribute__((aligned(32)));
A Dehci.h31 } __attribute__ ((packed, aligned(4)));
73 } __attribute__ ((packed, aligned(4)));
/u-boot/arch/powerpc/include/asm/
A Dtypes.h12 } __attribute__((aligned(16))) vector128;
/u-boot/arch/arm/cpu/armv7/
A Dsctlr.S19 bic r0, r0, #2 @ clear aligned flag
/u-boot/drivers/ata/
A Dsata_sil.h50 } __attribute__ ((aligned(8), packed));
60 } __attribute__ ((aligned(8), packed));
/u-boot/arch/arm/cpu/arm11/
A Dsctlr.S22 bic r0, r0, #2 @ clear aligned flag
/u-boot/board/st/common/
A DKconfig16 Each partition need to be aligned with the device erase block size,
26 Each partition need to be aligned with the device erase block size,
36 Each partition need to be aligned with the device erase block size,
/u-boot/arch/x86/include/asm/
A Dmp.h57 } __attribute__((aligned(ARCH_DMA_MINALIGN)));
/u-boot/include/xen/arm/
A Dinterface.h15 #define uint64_aligned_t u64 __attribute__((aligned(8)))
/u-boot/drivers/net/fsl-mc/
A DKconfig22 Reserved memory needs to be aligned for MC to use. Default value
/u-boot/include/linux/
A Drbtree.h28 } __attribute__((aligned(sizeof(long))));
/u-boot/doc/api/
A Dlinker_lists.rst110 a size of 16 then it will start at an 8-byte aligned offset, but not a
111 16-byte aligned offset.
126 to be aligned at the 'struct driver' alignment, which is 16 bytes. If the
/u-boot/board/armltd/integrator/
A Dpci.c60 #error PCI_BUS_NONMEM_START must be megabyte aligned
63 #error PCI_BUS_PREMEM_START must be megabyte aligned
/u-boot/common/
A Dlcd.c745 int aligned; in on_splashimage() local
752 aligned = (addr % 4 == 2); in on_splashimage()
753 if (!aligned) { in on_splashimage()
/u-boot/doc/device-tree-bindings/
A Dconfig.txt43 LBA-aligned will be rounded up to the next LBA address.

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