Searched refs:ana_pll (Results 1 – 3 of 3) sorted by relevance
79 pll_base = &ana_pll->dram_pll_gnrl_ctl; in fracpll_configure()82 pll_base = &ana_pll->video_pll1_gnrl_ctl; in fracpll_configure()177 pll_div_ctl = &ana_pll->sys_pll1_div_ctl; in intpll_configure()186 pll_div_ctl = &ana_pll->sys_pll2_div_ctl; in intpll_configure()195 pll_div_ctl = &ana_pll->sys_pll3_div_ctl; in intpll_configure()199 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; in intpll_configure()200 pll_div_ctl = &ana_pll->arm_pll_div_ctl; in intpll_configure()204 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; in intpll_configure()205 pll_div_ctl = &ana_pll->gpu_pll_div_ctl; in intpll_configure()209 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; in intpll_configure()[all …]
31 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()102 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll()103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()104 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll()117 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); in decode_sscg_pll()118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()119 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); in decode_sscg_pll()124 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0); in decode_sscg_pll()664 pll_cfg0 = &ana_pll->arm_pll_cfg0; in frac_pll_init()[all …]
376 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; in get_cpu_rev() local377 u32 reg = readl(&ana_pll->digprog); in get_cpu_rev()
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