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Searched refs:apllcsr (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dscg.h297 u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */ member
/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c522 reg = readl(&scg1_regs->apllcsr); in decode_pll()

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