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Searched refs:as_bus_params (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_topology.c86 iface_params->as_bus_params[i].cs_bitmask = val; in mv_ddr_topology_map_update()
106 iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1; in mv_ddr_topology_map_update()
221 VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs); in mv_ddr_cs_num_get()
A Dddr3_training.c194 as_bus_params[sphy].is_dqs_swap == 1) { in ddr3_tip_pad_inv()
486 as_bus_params[bus_cnt].cs_bitmask; in hws_ddr3_tip_init_controller()
699 as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
706 as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
713 as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
720 as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
742 as_bus_params[0].cs_bitmask != in ddr3_tip_rev3_rank_control()
744 as_bus_params[bus_cnt].cs_bitmask) || in ddr3_tip_rev3_rank_control()
755 as_bus_params[0].cs_bitmask; in ddr3_tip_rev3_rank_control()
757 as_bus_params[0].mirror_enable_bitmask << 4; in ddr3_tip_rev3_rank_control()
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A Dddr_topology_def.h41 struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM]; member
A Dddr3_debug.c1317 as_bus_params[uj].cs_bitmask); in print_topology()
1320 as_bus_params[uj].mirror_enable_bitmask); in print_topology()
1323 interface_params[ui].as_bus_params[uj]. in print_topology()
1327 interface_params[ui].as_bus_params[uj]. in print_topology()
A Dddr3_training_leveling.c787 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
789 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
793 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
A Dmv_ddr_plat.c1157 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()

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