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/u-boot/arch/xtensa/include/asm/
A Dasmmacro.h59 loop \at, 99f
67 extui \at, \at, \incr_log2, \mask_log2
69 srli \at, \at, \incr_log2
72 loop\cond \at, 99f
77 sub \at, \as, \ar
79 addi \at, \at, (1 << \incr_log2) - 1
80 srli \at, \at, \incr_log2
82 loop \at, 99f
114 b\ncond \at, 99f
118 slli \at, \at, \incr_log2
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A Dcacheasm.h50 __endla \ar, \at, 4 << (\line_width)
57 extui \at, \ar, 0, \line_width
58 add \as, \as, \at
60 __loops \ar, \as, \at, \line_width
62 __endla \ar, \at, (1 << (\line_width))
76 __endla \ar, \at, 4 << (\line_width)
81 .macro ___unlock_dcache_all ar at
90 .macro ___unlock_icache_all ar at
108 .macro ___flush_dcache_all ar at
117 .macro ___invalidate_dcache_all ar at
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/u-boot/board/imgtec/xilfpga/
A DREADME20 - 128Mbyte DDR RAM at 0x0000_0000
21 - 8Kbyte RAM at 0x1000_0000
22 - axi_intc at 0x1020_0000
23 - axi_uart16550 at 0x1040_0000
24 - axi_gpio at 0x1060_0000
25 - axi_i2c at 0x10A0_0000
26 - custom_gpio at 0x10C0_0000
27 - axi_ethernetlite at 0x10E0_0000
28 - 8Kbyte BootRAM at 0x1FC0_0000
29 - 16Mbyte QPI at 0x1D00_0000
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/u-boot/doc/uImage.FIT/
A Dcommand_syntax_extensions.txt29 2. bootm <addr1> /* single image at <addr1> */
30 3. bootm <addr1> /* multi-image at <addr1> */
31 4. bootm <addr1> - /* multi-image at <addr1> */
51 Ad. 2. Boot kernel image located at <addr1>.
71 from the image at <addr2>.
97 at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
102 at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
111 at <addr1>, without initrd, and pass FDT blob <subimg3> from the image at
148 at 200000:
152 some other new uImage stored at address 800000:
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/u-boot/doc/board/atmel/
A Dat91ek.rst20 U-Boot environment variables can be stored at different places:
26 You can choose your storage location at config step (here for at91sam9260ek)::
44 U-Boot environment variables can be stored at different places:
50 You can choose your storage location at config step (here for at91sam9260ek)::
67 U-Boot environment variables can be stored at different places:
79 You can choose to boot directly from U-Boot at config step::
93 U-Boot environment variables can be stored at different places:
112 U-Boot environment variables can be stored at different places:
131 U-Boot environment variables can be stored at different places:
154 U-Boot environment variables can be stored at different places:
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/u-boot/drivers/ram/aspeed/
A DKconfig19 bool "DDR4 targets at 400Mbps"
22 select DDR4 target data rate at 400M
25 bool "DDR4 targets at 800Mbps"
28 select DDR4 target data rate at 800M
31 bool "DDR4 targets at 1333Mbps"
34 select DDR4 target data rate at 1333M
37 bool "DDR4 targets at 1600Mbps"
40 select DDR4 target data rate at 1600M
/u-boot/board/freescale/mpc8349itx/
A DREADME36 U4 is located at address FE000000 and flash chip U7 is at FE800000.
37 If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
61 at which address. When J22.E is switched, addresses from FE000000
64 On the ITX, at the normal boot address (aka HIGHBOOT):
72 On the ITX, at the low boot address (LOWBOOT)
137 image at address FEF00000.
144 1) Build an ITX image to be loaded at FEF00000
150 2) Take the u-boot.bin image and flash it at FEF00000.
157 3) Build an ITX image to be loaded at FE000000
163 4) Take the u-boot.bin image and flash it at FE000000.
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/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.lsch3_218 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
19 - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
20 - Region 3 is at address 0x60_0000_0000 to the top of memory,
/u-boot/tools/binman/test/
A D098_4gb_and_skip_at_start_together.dts15 end-at-4gb;
16 skip-at-start = <0xffffffe0>;
/u-boot/board/work-microwave/work_92105/
A DREADME24 1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0.
38 at offset 0x00040000 in NAND.
52 in NAND at addresses 0x00000000 and 0x00020000
66 NAND at offset 00x00000000.
77 (load lpc32xx-full.bin at location $loadaddr)
83 (load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr)
90 (load u-boot.img at location $loadaddr)
/u-boot/arch/x86/include/asm/acpi/
A Dpcr.asl10 * Calculate PCR register base at specified PID
20 * Read a PCR register at specified PID and offset
35 * AND a value with PCR register at specified PID and offset
59 * OR a value with PCR register at specified PID and offset
/u-boot/doc/SPI/
A DREADME.ti_qspi_dra_test2 Simple steps used to test the QSPI at U-Boot
24 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c0…
43 on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
45 find a U-Boot image header at offset 0x20000 (set in the config file)
/u-boot/doc/device-tree-bindings/net/
A Dallwinner,sun4i-mdio.txt11 Example at the SoC level:
19 And at the board level:
/u-boot/doc/
A DREADME.arm-caches13 Enabling Caches at System Startup:
38 memory DMA buffer) should be aligned to cache-line boundary both at
39 at the beginning and at the end of the buffer.
41 to the aligned part. That is, one cache-line at the respective boundary
A DREADME.sha111 sha1 address len [addr] calculate the SHA1 sum [save at addr]
30 (for this example we use the Image from Flash, stored at 0xfffa0000 and
36 The SHA1 sum is stored in Flash at:
48 the calculated checksum at the right place:
A DREADME.pxe27 held in memory at once. The exact number and size of the files varies with
49 read in more detail about it at:
79 kernel_addr_r, initrd_addr_r - locations in RAM at which 'pxe boot' will
84 fdt_addr_r - location in RAM at which 'pxe boot' will store the fdt blob it
93 fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'.
100 with # are treated as comments. White space between and at the beginning of
119 menu include <path> - use tftp to retrieve the pxe file at <path>, which
143 (or FIT image) at <path>. it will be stored at the address
155 overlay(s) at <path>. it will be temporarily stored at the
164 at <path>. it will be stored at the address indicated in
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A DREADME.falcon45 If a valid uImage is not found at the defined location, U-Boot will be
89 A board may chose to look at the environment for decisions about falcon
120 storage can not be predicted nor provided at commandline, it depends
122 However at the end of an succesful 'spl export' run it will print the
136 using FDT is at the moment untested. The ppc port (see a3m071 example
164 Now the kernel is in RAM at address 0x82000000
167 ## Booting kernel from Legacy Image at 82000000 ...
178 Argument image is now in RAM at: 0x80000100
180 The result can be checked at address 0x80000100:
193 Now the parameters are stored into the NAND flash at the address
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/u-boot/doc/board/intel/
A Dbayleybay.rst8 Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
12 Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
16 from the sample SPI image provided in the FSP (SPI.bin at the time of writing)::
/u-boot/board/ti/ks2_evm/
A DREADME7 Documentation for this board can be found at
13 More details on these SoCs are available at company websites
17 The K2E SoC details are available at
20 The K2L SoC details are available at
23 The K2G SoC details are available at
46 The port related files can be found at following folders
91 on EVM. Follow instructions at
102 configuration as instructed at http://processors.wiki.ti.com/index.php/
149 to "SPI Little Endian Boot mode" as per instruction at
169 to "ARM NAND Boot mode" as per instruction at
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/u-boot/arch/arm/mach-sunxi/
A Drmr_switch.S6 @ at some point.
10 @ The address at which execution starts after the reset is held in the
14 @ This code below switches to AArch64 and starts execution at the specified
22 @ The resulting words should be inserted into the U-Boot file at
/u-boot/doc/device-tree-bindings/cpu/
A Dfsl,mpc83xx.txt15 - clocks: has to have two entries, which must be the core clock at index 0 and
16 the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable
/u-boot/doc/usage/
A Dbooti.rst40 size of the compressed file. The value has to be at least the size of
59 ## Flattened Device Tree blob at 08008000
60 Booting using the fdt blob at 0x8008000
88 ## Flattened Device Tree blob at 08008000
89 Booting using the fdt blob at 0x8008000
/u-boot/board/technexion/pico-imx6ul/
A DREADME26 Figure 6a at page 7).
95 Write the kernel at 2MB offset:
103 ## Booting kernel from Legacy Image at 82000000 ...
110 ## Flattened Device Tree blob at 83000000
111 Booting using the fdt blob at 0x83000000
113 Using Device Tree in place at 83000000, end 83009c63
116 Using Device Tree in place at 83000000, end 8300cc63
158 [ 0.000000] cma: Reserved 64 MiB at 0x8c000000
/u-boot/arch/arm/dts/
A Domap54xx-clocks.dtsi121 ti,index-starts-at-one;
164 ti,index-starts-at-one;
194 ti,index-starts-at-one;
219 ti,index-starts-at-one;
228 ti,index-starts-at-one;
237 ti,index-starts-at-one;
246 ti,index-starts-at-one;
255 ti,index-starts-at-one;
264 ti,index-starts-at-one;
273 ti,index-starts-at-one;
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/u-boot/drivers/power/
A DKconfig93 Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
110 Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to
128 Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to
147 Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to
161 Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
173 Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
189 Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to
205 Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
262 Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to
271 Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
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