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Searched refs:base_reg (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/pinctrl/broadcom/
A Dpinctrl-bcm283x.c27 u32 *base_reg; member
42 clrsetbits_le32(&priv->base_reg[reg_offset], in bcm2835_gpio_set_func_id()
52 val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]); in bcm2835_gpio_get_func_id()
113 priv->base_reg = dev_read_addr_ptr(dev); in bcm283x_pinctl_of_to_plat()
114 if (!priv->base_reg) { in bcm283x_pinctl_of_to_plat()
/u-boot/drivers/pinctrl/mvebu/
A Dpinctrl-mvebu.c51 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG, in mvebu_pinctl_emmc_set_mux()
58 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG, in mvebu_pinctl_emmc_set_mux()
116 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
177 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
197 priv->base_reg = dev_read_addr_ptr(dev); in mvebu_pinctl_probe()
198 if (!priv->base_reg) { in mvebu_pinctl_probe()
A Dpinctrl-mvebu.h23 void *base_reg; member
/u-boot/arch/arm/mach-tegra/
A Dclock.c594 u32 base_reg, misc_reg; in clock_set_rate() local
600 base_reg = readl(&pll->pll_base); in clock_set_rate()
604 base_reg |= m << pllinfo->m_shift; in clock_set_rate()
607 base_reg |= n << pllinfo->n_shift; in clock_set_rate()
618 base_reg |= PLL_ENABLE_MASK; in clock_set_rate()
626 base_reg |= PLL_BYPASS_MASK; in clock_set_rate()
627 writel(base_reg, &pll->pll_base); in clock_set_rate()
636 base_reg |= PLL_ENABLE_MASK; in clock_set_rate()
637 writel(base_reg, &pll->pll_base); in clock_set_rate()
640 base_reg &= ~PLL_BYPASS_MASK; in clock_set_rate()
[all …]
/u-boot/drivers/pci/
A Dpcie_iproc.c57 #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2) argument

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