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Searched refs:bic (Results 1 – 25 of 35) sorted by relevance

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/u-boot/arch/arm/mach-orion5x/
A Dlowlevel_init.S175 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
176 bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
177 bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
178 bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
197 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
198 bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
199 bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
200 bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
224 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
225 bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
[all …]
/u-boot/arch/arm/cpu/arm926ejs/
A Dstart.S41 bic r0,r0,#0x1f
90 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
91 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
95 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
/u-boot/board/samsung/goni/
A Dlowlevel_init.S61 bic r1, r1, #(1 << 1)
88 bic r1, r1, #0x1
93 bic r1, r1, #0x1
98 bic r1, r1, #0x1
103 bic r1, r1, #0x1
108 bic r1, r1, #0x1
113 bic r1, r1, #0x1
118 bic r1, r1, #0x1
123 bic r1, r1, #0x1
128 bic r1, r1, #0x1
[all …]
/u-boot/arch/arm/cpu/arm946es/
A Dstart.S40 bic r0,r0,#0x1f
86 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
87 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
/u-boot/arch/arm/cpu/arm1136/
A Dstart.S37 bic r0,r0,#0x1f
78 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
79 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
/u-boot/arch/arm/cpu/arm1176/
A Dstart.S49 bic r0, r0, #0x3f
84 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
85 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
/u-boot/arch/arm/cpu/pxa/
A Dstart.S44 bic r0,r0,#0x1f
108 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
109 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
139 bic r0, #0x1b00
140 bic r0, #0x0087
/u-boot/arch/arm/cpu/arm920t/
A Dstart.S34 bic r0, r0, #0x1f
94 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
95 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
/u-boot/arch/arm/include/asm/arch-mx6/
A Dmx6_plugin.S94 bic r0, r0, #(1 << 2) /* disable D Cache */
95 bic r0, r0, #0x1 /* clear bit 0 ; MMU off */
97 bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */
98 bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */
/u-boot/arch/arm/cpu/sa1100/
A Dstart.S34 bic r0,r0,#0x1f
113 bic r0, r0, #0x00002000 @ clear bit 13 (X)
114 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
/u-boot/arch/arm/cpu/armv7/
A Dlowlevel_init.S33 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
45 bic sp, sp, #7
A Dsctlr.S19 bic r0, r0, #2 @ clear aligned flag
A Dstart.S72 bic r0, #CR_V @ V = 0
154 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
155 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
159 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
214 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
/u-boot/arch/arm/lib/
A Dmuldi3.S33 bic xl, xl, ip, lsl #16
34 bic yl, yl, yh, lsl #16
A Dcrt0.S104 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
128 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
A Dcrt0_64.S86 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
104 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
/u-boot/arch/arm/cpu/arm926ejs/spear/
A Dspr_lowlevel_init.S35 bic r1, r1, r2
40 bic r1, r1, r2
87 bic r1,r1,r2
117 bic r1, r1, r2
/u-boot/arch/arm/cpu/armv8/
A Dlowlevel_init.S20 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
/u-boot/arch/arm/cpu/arm920t/ep93xx/
A Dlowlevel_init.S247 bic r0, r0, #EP93XX_LED_GREEN_ON
371 bic r1, r1, #EP93XX_LED_RED_ON
382 bic r1, r1, #EP93XX_LED_GREEN_ON
394 bic r1, r1, #EP93XX_LED_GREEN_ON
406 bic r0, r0, #EP93XX_LED_RED_ON
/u-boot/arch/arm/cpu/arm11/
A Dsctlr.S22 bic r0, r0, #2 @ clear aligned flag
/u-boot/drivers/sound/
A Drt5677.c95 static int rt5677_bic_or(struct rt5677_priv *priv, uint reg, uint bic, in rt5677_bic_or() argument
105 new_value = (old & ~bic) | (set & bic); in rt5677_bic_or()
/u-boot/arch/arm/cpu/arm720t/
A Dstart.S32 bic r0,r0,#0x1f
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dstart.S69 bic r2, r2, #0x1f
/u-boot/arch/arm/mach-uniphier/arm32/
A Dpsci_smp.S16 bic r1, r1, #(CR_C | CR_M) @ Disable MMU and Dcache
A Dlowlevel_init.S43 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
54 bic r0, r0, #0x37

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