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/u-boot/board/keymile/km_arm/
A Dkwbimage_128M16_1.cfg52 # bit 2-0: 3, Reserved
53 # bit 5-3: 3, Reserved
54 # bit 6: 0, Reserved
56 # bit 10-8: 3, Reserved
57 # bit 13-11: 3, Reserved
58 # bit 14: 0, Reserved
65 # bit 7-4: 6, Reserve
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
206 # bit 3-0: 2, M_ODT assertion same as bit 11-8
[all …]
A Dkwbimage_256M8_1.cfg52 # bit 2-0: 3, Reserved
53 # bit 5-3: 3, Reserved
54 # bit 6: 0, Reserved
56 # bit 10-8: 3, Reserved
57 # bit 13-11: 3, Reserved
58 # bit 14: 0, Reserved
83 # bit 31-20: ?,Reserved
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
206 # bit 3-0: 2, M_ODT assertion same as bit 11-8
[all …]
/u-boot/include/dt-bindings/mfd/
A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument
86 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument
87 #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) argument
112 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) argument
113 #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) argument
A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) argument
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) argument
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) argument
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) argument
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) argument
92 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) argument
101 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) argument
120 #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) argument
136 #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) argument
/u-boot/drivers/pinctrl/rockchip/
A Dpinctrl-rv1108.c21 .bit = 0,
27 .bit = 2,
33 .bit = 4,
39 .bit = 6,
45 .bit = 8,
69 .bit = 0,
75 .bit = 2,
86 u8 bit; in rv1108_set_mux() local
194 u8 bit; in rv1108_set_drive() local
247 u8 bit; in rv1108_set_schmitt() local
[all …]
A Dpinctrl-rk3308.c21 .bit = 12,
27 .bit = 0,
33 .bit = 4,
39 .bit = 8,
45 .bit = 12,
51 .bit = 0,
57 .bit = 4,
63 .bit = 8,
69 .bit = 8,
260 u8 bit; in rk3308_set_mux() local
[all …]
A Dpinctrl-rk3328.c21 .bit = 8,
27 .bit = 0,
33 .bit = 14,
132 u8 bit; in rk3328_set_mux() local
184 u8 bit, type; in rk3328_set_pull() local
200 data |= (ret << bit); in rk3328_set_pull()
210 int *reg, u8 *bit) in rk3328_calc_drv_reg_and_bit() argument
229 u8 bit; in rk3328_set_drive() local
241 data |= (ret << bit); in rk3328_set_drive()
274 u8 bit; in rk3328_set_schmitt() local
[all …]
A Dpinctrl-rk3368.c21 u8 bit; in rk3368_set_mux() local
32 data = (mask << (bit + 16)); in rk3368_set_mux()
33 data |= (mux & mask) << bit; in rk3368_set_mux()
44 int *reg, u8 *bit) in rk3368_calc_pull_reg_and_bit() argument
64 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
72 u8 bit, type; in rk3368_set_pull() local
88 data |= (ret << bit); in rk3368_set_pull()
99 int *reg, u8 *bit) in rk3368_calc_drv_reg_and_bit() argument
118 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
127 u8 bit; in rk3368_set_drive() local
[all …]
A Dpinctrl-rk3288.c39 u8 bit; in rk3288_set_mux() local
62 data &= ~(mask << bit); in rk3288_set_mux()
65 data = (mask << (bit + 16)); in rk3288_set_mux()
68 data |= (mux & mask) << bit; in rk3288_set_mux()
79 int *reg, u8 *bit) in rk3288_calc_pull_reg_and_bit() argument
99 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
107 u8 bit, type; in rk3288_set_pull() local
130 data |= (ret << bit); in rk3288_set_pull()
141 int *reg, u8 *bit) in rk3288_calc_drv_reg_and_bit() argument
169 u8 bit; in rk3288_set_drive() local
[all …]
A Dpinctrl-px30.c82 u8 bit; in px30_set_mux() local
144 u8 bit, type; in px30_set_pull() local
160 data |= (ret << bit); in px30_set_pull()
202 u8 bit; in px30_set_drive() local
216 switch (bit) { in px30_set_drive()
242 bit -= 16; in px30_set_drive()
246 bit, drv_type); in px30_set_drive()
263 data |= (ret << bit); in px30_set_drive()
278 int *reg, u8 *bit) in px30_calc_schmitt_reg_and_bit() argument
304 u8 bit; in px30_set_schmitt() local
[all …]
A Dpinctrl-rk3188.c21 u8 bit; in rk3188_set_mux() local
30 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); in rk3188_set_mux()
32 data = (mask << (bit + 16)); in rk3188_set_mux()
33 data |= (mux & mask) << bit; in rk3188_set_mux()
44 int *reg, u8 *bit) in rk3188_calc_pull_reg_and_bit() argument
54 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; in rk3188_calc_pull_reg_and_bit()
55 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3188_calc_pull_reg_and_bit()
70 *bit = 7 - (pin_num % ROCKCHIP_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
71 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3188_calc_pull_reg_and_bit()
80 u8 bit, type; in rk3188_set_pull() local
[all …]
A Dpinctrl-rk3128.c20 .bit = 0,
26 .bit = 4,
32 .bit = 8,
38 .bit = 12,
44 .bit = 12,
108 u8 bit; in rk3128_set_mux() local
131 data = (mask << (bit + 16)); in rk3128_set_mux()
144 int *reg, u8 *bit) in rk3128_calc_pull_reg_and_bit() argument
161 u8 bit; in rk3128_set_pull() local
169 data = BIT(bit + 16); in rk3128_set_pull()
[all …]
A Dpinctrl-rk3399.c61 u8 bit; in rk3399_set_mux() local
93 int *reg, u8 *bit) in rk3399_calc_pull_reg_and_bit() argument
123 u8 bit, type; in rk3399_set_pull() local
139 data |= (ret << bit); in rk3399_set_pull()
147 int *reg, u8 *bit) in rk3399_calc_drv_reg_and_bit() argument
161 *bit = (pin_num % 8) * 3; in rk3399_calc_drv_reg_and_bit()
172 u8 bit; in rk3399_set_drive() local
186 switch (bit) { in rk3399_set_drive()
212 bit -= 16; in rk3399_set_drive()
216 bit, drv_type); in rk3399_set_drive()
[all …]
A Dpinctrl-rk322x.c152 u8 bit; in rk3228_set_mux() local
172 data = (mask << (bit + 16)); in rk3228_set_mux()
173 data |= (mux & mask) << bit; in rk3228_set_mux()
183 int *reg, u8 *bit) in rk3228_calc_pull_reg_and_bit() argument
193 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3228_calc_pull_reg_and_bit()
201 u8 bit, type; in rk3228_set_pull() local
217 data |= (ret << bit); in rk3228_set_pull()
227 int *reg, u8 *bit) in rk3228_calc_drv_reg_and_bit() argument
237 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; in rk3228_calc_drv_reg_and_bit()
246 u8 bit; in rk3228_set_drive() local
[all …]
A Dpinctrl-rk3036.c21 u8 bit; in rk3036_set_mux() local
30 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); in rk3036_set_mux()
32 data = (mask << (bit + 16)); in rk3036_set_mux()
33 data |= (mux & mask) << bit; in rk3036_set_mux()
45 int *reg, u8 *bit) in rk3036_calc_pull_reg_and_bit() argument
54 *bit = pin_num % RK3036_PULL_PINS_PER_REG; in rk3036_calc_pull_reg_and_bit()
62 u8 bit; in rk3036_set_pull() local
69 rk3036_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit); in rk3036_set_pull()
70 data = BIT(bit + 16); in rk3036_set_pull()
72 data |= BIT(bit); in rk3036_set_pull()
/u-boot/arch/mips/
A Dconfig.mk7 32bit-emul := elf32btsmip
8 64bit-emul := elf64btsmip
9 32bit-bfd := elf32-tradbigmips
10 64bit-bfd := elf64-tradbigmips
16 32bit-emul := elf32ltsmip
17 64bit-emul := elf64ltsmip
18 32bit-bfd := elf32-tradlittlemips
19 64bit-bfd := elf64-tradlittlemips
27 OBJCOPYFLAGS += -O $(32bit-bfd)
33 KBUILD_LDFLAGS += -m$(64bit-emul)
[all …]
/u-boot/drivers/pinctrl/meson/
A Dpinctrl-meson.c111 *bit = desc->bit + pin - bank->first; in meson_gpio_calc_reg_and_bit()
123 &bit); in meson_gpio_get()
137 &bit); in meson_gpio_set()
141 clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0); in meson_gpio_set()
153 &bit); in meson_gpio_get_direction()
169 &bit); in meson_gpio_direction_input()
186 &bit); in meson_gpio_direction_output()
193 &bit); in meson_gpio_direction_output()
220 clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), BIT(bit)); in meson_pinconf_bias_set()
250 bit = bit << 1; in meson_pinconf_drive_strength_set()
[all …]
/u-boot/fs/yaffs2/
A Dyaffs_ecc.c153 unsigned bit; in yaffs_ecc_correct() local
155 bit = byte = 0; in yaffs_ecc_correct()
175 bit |= 0x04; in yaffs_ecc_correct()
177 bit |= 0x02; in yaffs_ecc_correct()
179 bit |= 0x01; in yaffs_ecc_correct()
181 data[byte] ^= (1 << bit); in yaffs_ecc_correct()
238 unsigned bit; in yaffs_ecc_correct_other() local
252 bit = 0; in yaffs_ecc_correct_other()
255 bit |= 0x04; in yaffs_ecc_correct_other()
257 bit |= 0x02; in yaffs_ecc_correct_other()
[all …]
/u-boot/arch/arm/dts/
A Domap3xxx-clocks.dtsi28 ti,bit-shift = <6>;
39 ti,bit-shift = <7>;
88 ti,bit-shift = <4>;
102 ti,bit-shift = <2>;
116 ti,bit-shift = <6>;
143 ti,bit-shift = <2>;
248 ti,bit-shift = <16>;
355 ti,bit-shift = <6>;
363 ti,bit-shift = <8>;
390 ti,bit-shift = <5>;
[all …]
A Domap36xx-clocks.dtsi22 ti,bit-shift = <0x1e>;
25 ti,set-bit-to-disable;
32 ti,bit-shift = <0x1b>;
34 ti,set-bit-to-disable;
41 ti,bit-shift = <0xc>;
43 ti,set-bit-to-disable;
50 ti,bit-shift = <0x1c>;
52 ti,set-bit-to-disable;
59 ti,bit-shift = <0x1f>;
61 ti,set-bit-to-disable;
[all …]
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_pbs.c101 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
219 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
378 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
408 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
528 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
631 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
708 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
760 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
774 [bit])); in ddr3_tip_pbs()
963 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_print_pbs_result()
[all …]
/u-boot/drivers/gpio/
A Ddb8500_gpio.c88 u32 bit = 1 << offset; in gpio_set_mode() local
91 afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit; in gpio_set_mode()
94 afunc |= bit; in gpio_set_mode()
96 bfunc |= bit; in gpio_set_mode()
119 u32 bit = 1 << offset; in db8500_gpio_set_pull() local
124 pdis |= bit; in db8500_gpio_set_pull()
126 pdis &= ~bit; in db8500_gpio_set_pull()
130 writel(bit, addr + DB8500_GPIO_DATS); in db8500_gpio_set_pull()
132 writel(bit, addr + DB8500_GPIO_DATC); in db8500_gpio_set_pull()
147 u32 bit = 1 << offset; in db8500_gpio_get_input() local
[all …]
/u-boot/doc/device-tree-bindings/timer/
A Datcpit100_timer.txt11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM
/u-boot/arch/sandbox/
A DKconfig14 bool "Use 64-bit addresses"
26 32bit sandbox.
37 prompt "Run sandbox on 32/64-bit host"
40 Sandbox can be built on 32-bit and 64-bit hosts.
41 The default is to build on a 64-bit host and run
42 on a 64-bit host. If you want to run sandbox on
43 a 32-bit host, change it here.
46 bool "32-bit host"
50 bool "64-bit host"

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