| /u-boot/drivers/video/ |
| A D | mxsfb.c | 98 switch (bpp) { in mxs_lcd_init()
181 int bpp, u32 fb) in mxs_probe_common() argument
184 mxs_lcd_init(dev, fb, timings, bpp); in mxs_probe_common()
245 int bpp = -1; in video_hw_init() local
261 bpp = video_get_params(&mode, penv); in video_hw_init()
271 switch (bpp) { in video_hw_init()
324 u32 *bpp) in mxs_of_get_timings() argument
364 u32 bpp = 0; in mxs_video_probe() local
379 switch (bpp) { in mxs_video_probe()
415 u32 bpp = 0; in mxs_video_bind() local
[all …]
|
| A D | anx9804.h | 19 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
22 int bpp) {} in anx9804_init() argument
|
| A D | ati_radeon_fb.c | 48 #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ argument
50 #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ argument
51 ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
361 void radeon_setmode_9200(int vesa_idx, int bpp) in radeon_setmode_9200() argument
370 switch (bpp) { in radeon_setmode_9200()
408 switch (bpp) { in radeon_setmode_9200()
439 switch (bpp) { in radeon_setmode_9200()
467 switch (bpp) { in radeon_setmode_9200()
501 switch (bpp) { in radeon_setmode_9200()
542 if (bpp > 8) in radeon_setmode_9200()
|
| A D | da8xx-fb.c | 485 u32 bpp, u32 raster_order) in lcd_cfg_frame_buffer() argument
532 if (bpp == 24) in lcd_cfg_frame_buffer()
534 else if (bpp == 32) in lcd_cfg_frame_buffer()
540 switch (bpp) { in lcd_cfg_frame_buffer()
672 u32 bpp; in lcd_init() local
712 bpp = cfg->bpp; in lcd_init()
714 bpp = cfg->p_disp_panel->max_bpp; in lcd_init()
715 if (bpp == 12) in lcd_init()
716 bpp = 16; in lcd_init()
928 da8xx_lcd_cfg->bpp); in video_hw_init()
[all …]
|
| A D | anx9804.c | 29 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) in anx9804_init() argument
37 if (bpp == 18) in anx9804_init()
|
| A D | bus_vcxk.c | 364 unsigned long bpp; in vcxk_display_bitmap() local
377 bpp = le16_to_cpu(bmp->header.bit_count); in vcxk_display_bitmap()
395 switch (bpp) { in vcxk_display_bitmap()
401 "not supported by VCxK\n", bpp); in vcxk_display_bitmap()
|
| A D | videomodes.c | 163 int bpp; in video_get_params() local
197 bpp = 24 - ((mode % 3) * 8); in video_get_params()
214 GET_OPTION ("depth:", bpp) in video_get_params()
219 return bpp; in video_get_params()
|
| A D | da8xx-fb.h | 75 int bpp; member
|
| /u-boot/board/friendlyarm/nanopi2/ |
| A D | lcds.c | 98 .bpp = 24,
125 .bpp = 24,
152 .bpp = 24,
179 .bpp = 24,
206 .bpp = 24,
233 .bpp = 24,
260 .bpp = 24,
286 .bpp = 24,
313 .bpp = 24,
339 .bpp = 24,
[all …]
|
| A D | nxp-fb.h | 67 int bpp; member
|
| /u-boot/include/ |
| A D | video_fb.h | 63 unsigned int bpp, /* bytes per pixel */
75 unsigned int bpp, /* bytes per pixel */
|
| A D | video_easylogo.h | 21 int bpp; member
|
| A D | phy-mipi-dphy.h | 279 unsigned int bpp,
|
| /u-boot/doc/device-tree-bindings/video/ |
| A D | sandbox-fb.txt | 7 log2-depth: Log base 2 of the U-Boot display buffer depth (4=16bpp, 5=32bpp).
|
| /u-boot/arch/arm/include/asm/arch-tegra20/ |
| A D | display.h | 15 unsigned bpp; /* Bits per pixel */ member
|
| /u-boot/drivers/video/ti/ |
| A D | tilcdc.h | 28 u32 bpp; member
|
| A D | am335x-fb.h | 48 unsigned int bpp; /* bits per pixel */ member
|
| A D | tilcdc.c | 216 switch (info.bpp) { in tilcdc_probe()
222 dev_err(dev, "invalid seting, bpp: %d\n", info.bpp); in tilcdc_probe()
292 reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3; in tilcdc_probe()
363 if (info.bpp == 24) in tilcdc_probe()
365 else if (info.bpp == 32) in tilcdc_probe()
376 uc_priv->bpix = log_2_n_round_up(info.bpp); in tilcdc_probe()
|
| A D | am335x-fb.c | 118 #define FBSIZE(x) (((x)->hactive * (x)->vactive * (x)->bpp) >> 3)
232 switch (panel->bpp) { in am335xfb_init()
242 pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp); in am335xfb_init()
254 panel->hactive, panel->vactive, panel->bpp, in am335xfb_init()
|
| /u-boot/board/siemens/rut/ |
| A D | board.c | 300 .bpp = 16,
316 .bpp = 16,
332 .bpp = 24,
467 lcd_cfgs[display].bpp); in board_video_init()
|
| /u-boot/drivers/phy/ |
| A D | phy-core-mipi-dphy.c | 20 unsigned int bpp, in phy_mipi_dphy_get_default_config() argument
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
|
| /u-boot/doc/device-tree-bindings/video/tilcdc/ |
| A D | panel.txt | 9 - bpp: Bits per pixel
43 bpp = <16>;
|
| /u-boot/drivers/video/bridge/ |
| A D | anx6345.c | 273 int ret, i, bpp; in anx6345_enable() local
342 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) { in anx6345_enable()
347 timing.hactive.typ, timing.vactive.typ, bpp); in anx6345_enable()
348 if (bpp == 6) in anx6345_enable()
|
| /u-boot/board/BuR/common/ |
| A D | common.c | 95 pnltmp.bpp = env_get_ulong("ds1_bpp", 10, ~0UL); in load_lcdtiming()
111 ~0UL == (pnltmp.bpp) || in load_lcdtiming()
138 pnltmp.hactive, pnltmp.vactive, pnltmp.bpp, in load_lcdtiming()
|
| /u-boot/board/siemens/pxm2/ |
| A D | board.c | 307 .bpp = 32,
423 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); in board_video_init()
425 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); in board_video_init()
|