Home
last modified time | relevance | path

Searched refs:bwcr (Results 1 – 11 of 11) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Ddram_sunxi_dw.c120 writel((1 << 16) | (400 << 0), &mctl_com->bwcr); in mctl_set_master_priority_h3()
145 writel((1 << 16) | (400 << 0), &mctl_com->bwcr); in mctl_set_master_priority_v3s()
169 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_a64()
196 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_h5()
224 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_r40()
A Ddram_sun8i_a23.c341 writel(0x00010138, &mctl_com->bwcr); in sunxi_dram_init()
A Ddram_sun8i_a83t.c272 writel(0x000101a0, &mctl_com->bwcr); in mctl_channel_init()
A Ddram_sun50i_h6.c132 writel(BIT(16), &mctl_com->bwcr); in mctl_set_master_priority()
A Ddram_sun50i_h616.c70 writel(BIT(16), &mctl_com->bwcr); in mctl_set_master_priority()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun50i_h616.h40 u32 bwcr; /* 0x200 bandwidth control register */ member
A Ddram_sun8i_a33.h55 u32 bwcr; /* 0x90 */ member
A Ddram_sunxi_dw.h23 u32 bwcr; /* 0x90 bandwidth control register */ member
A Ddram_sun8i_a83t.h55 u32 bwcr; /* 0x90 */ member
A Ddram_sun50i_h6.h45 u32 bwcr; /* 0x200 bandwidth control register */ member
A Ddram_sun8i_a23.h81 u32 bwcr; /* 0x90 */ member

Completed in 19 milliseconds