| /u-boot/board/keymile/kmp204x/ |
| A D | pbi.cfg | 10 091380c0 000009C4
12 091380c0 000009C4
14 091380c0 000009C4
17 091380c0 000009C4
19 091380c0 000009C4
21 091380c0 000009C4
23 091380c0 000009C4
25 091380c0 000009C4
27 091380c0 000009C4
29 091380c0 000009C4
[all …]
|
| /u-boot/arch/arm/mach-rmobile/ |
| A D | lowlevel_init_ca15.S | 14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
49 mcreq p15, 0, r0, c1, c0, 1
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
58 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
66 mcrne p15, 1, r0, c9, c0, 2
72 mrc p15, 0, r0, c1, c0, 1
74 mcr p15, 0, r0, c1, c0, 1
|
| /u-boot/arch/arm/cpu/armv7/ |
| A D | start.S | 46 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
71 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
78 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
153 mrc p15, 0, r0, c1, c0, 0
163 mcr p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
237 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
262 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
273 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
287 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
[all …]
|
| A D | cache_v7_asm.S | 27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
41 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
98 mrc p15, 1, r0, c0, c0, 1 @ read clidr
109 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
111 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
139 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
|
| A D | nonsec_virt.S | 32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
48 mcr p15, 0, r5, c12, c0, 1
61 mrc p15, 0, r5, c1, c0, 1
63 mcr p15, 0, r5, c1, c0, 1
68 mrc p15, 0, r5, c1, c0, 1
70 mcr p15, 0, r5, c1, c0, 1
93 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
118 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
193 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
197 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
[all …]
|
| A D | psci.S | 183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
207 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
232 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
240 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
242 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
250 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
252 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
265 mrc p15, 0, r0, c1, c0, 0 @ SCTLR
[all …]
|
| A D | sctlr.S | 18 mrc p15, 0, r0, c1, c0, 0 @ load system control register
20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
|
| /u-boot/arch/arm/cpu/armv7/sunxi/ |
| A D | fel_utils.S | 19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
21 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
23 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
35 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
37 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
|
| /u-boot/board/freescale/t104xrdb/ |
| A D | t104x_pbi_sb.cfg | 10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
38 091380c0 000FFFFF
|
| A D | t104x_pbi.cfg | 10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
|
| /u-boot/arch/arm/mach-uniphier/arm32/ |
| A D | lowlevel_init.S | 23 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 mcr p15, 0, r0, c1, c0, 0
42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
44 mcr p15, 0, r0, c1, c0, 0
53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
56 mcr p15, 0, r0, c2, c0, 2
59 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
76 mcr p15, 0, r0, c1, c0, 0
|
| A D | psci_smp.S | 14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
17 mcr p15, 0, r1, c1, c0, 0
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
|
| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | psci-suspend.S | 19 mcr p15, 2, r0, c0, c0, 0
20 mrc p15, 1, r0, c0, c0, 0
61 mcr p15, 0, r6, c1, c0, 0
|
| /u-boot/arch/arm/cpu/pxa/ |
| A D | start.S | 107 mrc p15, 0, r0, c1, c0, 0
111 mcr p15, 0, r0, c1, c0, 0
124 mrc p15, 0, \reg, c2, c0, 0
131 mcr p15, 0, r0, c3, c0, 0
135 mcr p15, 0, r0, c2, c0, 0
138 mrc p15, 0, r0, c1, c0, 0
143 mcr p15, 0, r0, c1, c0, 0
|
| /u-boot/arch/arm/mach-mediatek/mt7629/ |
| A D | lowlevel_init.S | 29 mcr p15, 0, r0, c14, c0, 0
44 mrc p15, 0, r0, c1, c0, 1
46 mcr p15, 0, r0, c1, c0, 1
49 mrc p15, 0, r0, c0, c0, 5
|
| /u-boot/arch/arm/mach-k3/ |
| A D | lowlevel_init.S | 11 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
|
| /u-boot/arch/arm/mach-mediatek/mt7623/ |
| A D | lowlevel_init.S | 18 mrc p15, 0, r0, c1, c0, 1
20 mcr p15, 0, r0, c1, c0, 1
|
| /u-boot/arch/arm/mach-zynq/ |
| A D | lowlevel_init.S | 13 mrc p15, 0, r1, c1, c0, 2
16 mcr p15, 0, r1, c1, c0, 2
|
| /u-boot/board/freescale/t4rdb/ |
| A D | t4_pbi.cfg | 11 091380c0 00000100
27 091380c0 00100000
|
| /u-boot/board/freescale/t102xrdb/ |
| A D | t1024_pbi.cfg | 5 091380c0 00000100
26 091380c0 000FFFFF
|
| /u-boot/arch/arm/cpu/arm11/ |
| A D | sctlr.S | 20 mrc p15, 0, r0, c1, c0, 0 @ load system control register
23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
|
| /u-boot/arch/arm/dts/ |
| A D | stih407-clock.dtsi | 98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
109 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
116 clk_s_c0_pll0: clk-s-c0-pll0 {
122 clock-output-names = "clk-s-c0-pll0-odf-0";
126 clk_s_c0_pll1: clk-s-c0-pll1 {
132 clock-output-names = "clk-s-c0-pll1-odf-0";
[all …]
|
| A D | stih410-clock.dtsi | 99 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
106 clock-output-names = "clk-s-c0-fs0-ch0",
107 "clk-s-c0-fs0-ch1",
108 "clk-s-c0-fs0-ch2",
109 "clk-s-c0-fs0-ch3";
110 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
117 clk_s_c0_pll0: clk-s-c0-pll0 {
123 clock-output-names = "clk-s-c0-pll0-odf-0";
127 clk_s_c0_pll1: clk-s-c0-pll1 {
133 clock-output-names = "clk-s-c0-pll1-odf-0";
[all …]
|
| /u-boot/arch/arm/cpu/arm926ejs/spear/ |
| A D | start.S | 54 mrc p15, 0, r0, c1, c0, 0
56 mcr p15, 0, r0, c1, c0, 0
|
| /u-boot/arch/arm/mach-aspeed/ast2600/ |
| A D | lowlevel_init.S | 93 mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ
112 mrc p15, 0, r0, c1, c0, 1
114 mcr p15, 0, r0, c1, c0, 1
120 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register
|